The present disclosure relates generally to electronic device displays, and, more particularly, to reducing a number of masks need to manufacture display panel thin film transistor (TFT) backplane.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
During the fabrication of electronic device displays, numerous masks may be used to define areas of deposition and/or etching to create patterned materials on the TFT backplanes. For example, materials may be dry-etched using a plasma etching machine on an area that is masked. Further wet-etching may pattern masked areas by use of certain chemicals, such as oxalic acid. Generally speaking, as the display panel TFT backplanes are fabricated, the number of masks may be directly proportional to the takt time, or overall completion time, needed to manufacture the display panel TFT backplane. As the number of masks increase, the takt time may increase due to, for example, mask alignment times and material preparation times (e.g., curing times) related to deposition and etching tasks associated with each mask. Increased takt times may result in certain inefficiencies, such as increased cost and reduced manufacturing capacity, which may result in manufacturing delays, etc.